About Me

I am researcher and lecturer ("enseignant-chercheur") at ENSTA-Bretagne, an engineering school located in Brest, France. I am also member of LabSticc , a major research laboratory in France.

My main research activities are related to Hardware-software Codesign of Embedded Systems and Cyber-physical systems (CPS) : modeling, DSL design, transformation, simulation, compilation onto real architectures organized around a network of processing elements like RISC processors, FPGAs, multicores, sensors and actuators. All these topics have no meaning without another keyword : Models of Computation (MoCs). As Wikipedia explains : in model-driven engineering, the model of computation explains how the behaviour of the whole system is the result of the behaviour of each of its components.

I am involved in many concrete designs in the field of multimedia, communication and robotics, that ensure that my research is still rooted in the ground.

I spent 10 years as IC Design Engineer for Thomson R & D France (now Technicolor) and I am cofounder of Modae Technologies, that delivered a high-level modeling, simulation and behavioral synthesis framework for FPGAs starting from Python and Ruby DSLs, as a possible alternative to Matlab/Simulink. Modae was awarded twice by the French Ministry of Research and OSEO (now Bpi France).

Journal publications

• High-level synthesis using hierarchical conditional dependency graphs in the CODESIS system. Apostolos A. Kountouris, Christophe Wolinski and Jean-Christophe Le Lann. Journal of Systems Architecture 47(3-4): 293-313 (2001)
• Polychrony for System Design. Paul Le Guernic, Jean-Pierre Talpin and Jean-Christophe Le Lann. Journal of Circuits, Systems, and Computers 12(3): 261-304 (2003)
• Model-Driven Toolset for Embedded Reconfigurable Cores: Flexible Prototyping and Software-like Debugging. L. Lagadec, C. Teodorov, J-C. Le Lann, D. Picard and E. Fabiani- Journal on Science of Computer Programming (JSCP) . 2014
• Extended overlay architectures for heterogeneous FPGA cluster management. Mohamad Najem, Theotime Bollengier, Jean-Christophe Le Lann, Loic Lagadec, Journal of System Architecture. 2017.
• Detection of AIS Messages Falsifications and Spoofing by Checking Messages Compliance with TDMA Protocol, M Louart, JJ Szkolnik, AO Boudraa, JC Le Lann, F Le Roy, Digital Signal Processing, 2023.

Book chapters

• Protecting Behavioral IPs During Design Time: Key-Based Obfuscation Techniques for HLS in the Cloud Behavioral Synthesis for Hardware Security - Springer 2022
• XPU: A C++ Metaprogramming Approach to Ease Parallelism Expression: Parallelization Methodology, Internal Design and Practical Application. Nader Khammassi, Jean-Christophe Le Lann. Parallel Programming: Practical Aspects, Models and Current Limitations", NOVA publishers, pp.175-198, 2014 [bib] [HAL]

Conference publications

2023
• Acceleration of contractor algebra on RISCV in the context of mobile robotic Pierre Filiol , Luc Jaulin, Jean-Christophe Le Lann, Théotime Bollengier Summer Workshop on Interval Methods, Jun 2023, Angers, France.

2022
• HLS-based Accelerated Simulation of Large Scale Cyber-Physical Systems on FPGAs Maélic Louart, Jean-Christophe Le Lann, Frédéric Le Roy, Jean-Jacques Szkolnik, Abdel Boudraa Newcas'22
• Emulation de Systèmes Cyber-Physiques sur FPGA Maélic Louart, Jean-Christophe Le Lann, Frédéric Le Roy, Jean-Jacques Szkolnik, Abdel Boudraa Gretsi'22 [pdf] [bib] [poster]
• A new type of intervals for solving problems involving partially defined functions. Pierre Filiol, Théotime Bollengier, Luc Jaulin, Jean-Christophe Le Lann 13th Summer Workshop on Interval Methods [pdf]
• Stratégie de détection des Falsifications des Positions des Messages AIS Basée sur l'Application du Filtre IMM. Maelic Louart, Jean-Jacques Szkolnik, Abdel Boudraa, Jean-Christophe Le Lann, Frédéric Le Roy. Gretsi'22 [pdf] [poster]

2021
• Opportunistic IP birthmarking using side effects of code transformations on high-level synthesis. Hannah Badier, Christian Pilato, Jean-Christophe Le Lann, Philippe Coussy, Guy Gogniat Date'21 [pdf] [bib]

2020
• Towards a Hardware DSL Ecosystem: RubyRTL and Friends. Jean-Christophe Le Lann and Hannah Badier, Florent Kermarrec OSDA Date'20 [pdf] [bib] [poster]

2019
• LiteX: an open-source SoC builder and library based on Migen Python DSL. Florent Kermarrec, Sébastien Bourdeauducq, Jean-Christophe Le Lann and Hannah Badier OSDA Date'19 [pdf] [bib]
• Transient Key-based Obfuscation for HLS in an Untrusted Cloud Environment. Hannah Badier, Jean-Christophe Le Lann, Philippe Coussy and Guy Gogniat. DATE'19 [pdf] [bib]

2018
• An integrated toolchain for overlay centric system-on-chip. Jean-Christophe Le Lann, Théotime Bollengier, Loic Lagadec, and Mohamad Najem, Recosoc'2018 [pdf] [bib]

2017
• A Cost-effective Approach for Efficient Time-sharing of Reconfigurable Architectures. Mohamad Najem, Theootime Bollengier,Jean-Christophe Le Lann, and Loic Lagadec FPGA4GPC'2017
• Soft timing closure for soft programmable logic cores: The ARGen approach. Theotime Bollengier, Loic Lagadec, Mohamad Najem, Jean-Christophe Le Lann and Pierre Guilloux ARC'2017

2016
• CaRDIN: An Agile Environment for Edge Computing on Reconfigurable Sensor Networks. Xuan Sang Le,Jean-Christophe Le Lann, Loic Lagadec, Luc Fabresse, Noury Bouraqadi, Jannik Laval. Int. Sym on Internet of Things \& Everything, Dec 2016, Las Vegas, United States. CSCI'16
• Speeding Up Robot Control Software Through Seamless Integration With FPGA. Xuan Sang LE, Luc Fabresse, Jannik Laval, Jean-Christophe Le Lann, Loic Lagadec, Noury Bouraqadi SHARC'16
• Overlay Architectures for Heterogeneous FPGA Cluster Management. Theotime Bollengier, Loic Lagadec, Mohamad Najem and Jean-Christophe Le Lann. DASIP'16 demo night
• Zeff : Une plateforme pour l’intégration d’architectures Overlay dans le Cloud. Theotime Bollengier, Mohamad Najem, Jean-Christophe Le Lann et Loic Lagadec COMPAS'16
• FPGAs in the Cloud: a Hybrid hardware/software Framework. Mohamad Najem, Theotime Bollengier, Jean-Christophe Le Lann, and Loic Lagadec GDR SoCSiP 2016: French research community in Systems on Chip.

2015
• Communication-aware parallelization strategies for high-performance applications, Imran Ashraf, Koen Bertels, Nader Khammassi, Jean-Christophe Le Lann, IEEE IVLSI,july [pdf]

2014
• Tackling Real-Time Signal Processing Applications on Shared Memory Multicore Architectures Using XPU. Nader Khammassi, Jean-Christophe Le Lann, Embedded Real-Time Software and Systems (ERTS)- February. Toulouse, France.[pdf]
• Design and implementation of a cache hierarchy-aware task scheduling for parallel loops on multicore architectures. Nader Khammassi, Jean-Christophe Le Lann. International conference on Parallel, Distributed Computing technologies and Applications (PDCTA) Sydney, Australia.[pdf]
• A High-Level Programming Model to Ease Pipeline Parallelism Expression on Shared Memory Multicore Architectures. Nader Khammassi, Jean-Christophe Le Lann. High Performance Computing Symposium (HPC) - April 2014 [pdf]
• A Prototyping Platform for Virtual Reconfigurable Units Lagadec L., Le Lann Jean-Christophe, Bollengier T. Recosoc 2014 - May, Montpellier France.

2013

• Early exploring design alternatives of smart sensor software with Model of Computation implemented with actors, Jean-Philippe Schneider, Zoe Drey, Jean-Christophe Le Lann ESUG 2013 - 21th International Smalltalk Conference, Annecy : France.
• Synthèse de controleurs numeriques par composition de contraintes applicatives et temporelles Philippe Dhaussy , Jean-Christophe Le Lann, Gretsi'13, Brest

2012

• MHPM: Multi-Scale Hybrid Programming Model: A Flexible Parallelization Methodology. Nader Khammassi, Jean-Christophe Le Lann, Jean-Philippe Diguet, Alexandre Skrzyniarz. HPCC-ICESS 2012: 71-80a [pdf]
• An experimental toolchain based on high-level dataflow models of computation for heterogeneous MPSoC. (Julien Heulot, Karol Desnos, Jean-François Nezan, Maxime Pelcat, Mickael Raulet, Herve Yviquel, P.-L. Lagalaye, J-C Le Lann. DASIP'12
• From system-level models to heterogeneous embedded systems, Jean-Christophe Le Lann, Joel Champeau, Papa Issa Diallo, Pierre-Laurent Lagalaye.RITF 2012 - Recherche et Innovation pour les Transports du Futur, Paris : France.a [paper][presentation]
• Modelisation algorithmique et synthèse d'architectures assistees par model-checking, Jean-Christophe Le Lann, Philippe Dhaussy, Pierre-Laurent Lagalaye.CAL 2012-, Montpellier : France (2012)[pdf]

2010

• MoPCoM Methodology: Focus on Models of Computation. Ali Koudri, Joel Champeau, Jean-Christophe Le Lann and Vincent Leilde. ECMFA'2010, Paris
• UML/MARTE Process for SoC/SoPC, (with Ali Koudri, Joel Champeau, and Denis Aulagnier), ERTS'2010, Toulouse
• JOG : une approche haut niveau des systèmes embarques via Armadeus et Java. Olivier Reynet, Jean-Christophe Le Lann, and Benoît Clement. Journees Demonstrateurs en robotique, Angers.(pdf)

2008

• Video Encoding Analysis for Parallel Execution on Reconfigurable Architectures. Muhammad Rashid, Jean-Christophe Le Lann and Koen Bertels. 6th Symposium on Design, Analysis, and Simulation of Distributed Systems 2008 June 16 - June 19, 2008, Edinburgh, UK (more)
• Using MARTE in the MOPCOM SoC/SoPC Methodology. Koudri A, Vojtsiek D, Soulard P, Moy C, Champeau J, Vidal J et Le Lann Jean-Christophe. DATE 2008.Munich.

2007

• A programming toolset enabling exploitation of reconfiguration for increased flexibility in future system-on-chips. G. Edelin, P. Bonnot, W. Gouja,K. Bertels, F. Thoma, A. Schneider,J. Knablein, B. Pottier and J-C Le Lann. DATE 2007, Aprl 16-20 2007, Nice, France
• CDFG Platform in MORPHEUS. Jalil Boukhobza, Loic Lagadec, Alain Plantec, Jean-Christophe Le Lann. AETHER - MORPHEUS Workshop AMWAS'07, Paris : France (2007)
• Loosely Coupled Accelerators for Reconfigurable SoC . Jean-Christophe Le LANN, Bernard POTTIER, Matthieu GODET and Ronan KERYELL. Technical Report, ENST Bretagne, May 2007. link

2002

• Jean-Christophe Le Lann. Simulation et synthèse de circuits s'appuyant sur le Modèle Synchrone. PhD Thesis Universite de Rennes 1, IFSIC, March 2002

1999

• J.C. Le Lann, C. Wolinski. Load Balancing and Functional Unit Assignment in High-Level Synthesis. In Proceedings of the SCI'99/ISAS'99, Orlando, Floride, August 1999

1998

• J.C. Le Lann. Generation automatique de code VHDL à partir de Signal. In Journees AAA98, CEA, Saclay, January 1998
• J.C. Le Lann. Operand Isolation Using Signal Clock Calculus. In Proceedings of the 1st UK Low-Power Workshop, Sheffield, UK, September 1998

1997

• Allemand, Michel, Francois Bodin, Apostolos Kountouris, Paul Le Guernic, Jean-Christophe Le Lann, Andre Seznec, and Christophe Wolinski. "A synchronous approach for hardware design." Publication Interne INRIA 1131 (1997)
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Patents

• (France Patent FR3115134) Procedé de configuration d'un circuit logique programmable.
• (France Patent 2978263-A1) Procede de synthèse de haut niveau d'une application . Jean-Christophe Le Lann, Pierre-Laurent Lagalaye.
• MPEG4/AVC/H.264 Context adaptive arithmetic decoding method and device. Le Lann, Jean-Christophe, Gildas Cocherel, Christophe Jollivet, and Mickael Fossard (WO/2007/118811)

Funded Research

IFEST 2010-2013 Artemis European project

• Integrated Toolchain developpement for the Design of Embedded System
• Based on State of the Art Model-driven developpment
• A top-ranked european project !

ANR MoPCoM-SoC 2008-2010 (site)

• Increasing productivity by reusing software techniques, architectures and/or components (targeting hardware or software components)
• Flexibility, interoperability, maintainability of applications and/or systems
• Ensuring the functionality of the systems

FP7 hARTES (site)

• Holistic approach for the design of complex and heterogeneous embedded solutions
• How to deal with the complexity of future multimedia devices ?
• A framework that allows novel algorithms for design space exploration

FP6 Morpheus 2008-2010 (Book)

• Design of a fully dynamically reconfigurable heterogeneous architecture
• ...downto a concrete SoC
• ...along with a complete compilation/synthesis toolchain